1. Field of the Invention
The present invention relates to a comparator for a pipelined analog-to-digital converter (ADC) and related signal sampling method, and more particularly, to a comparator that performs a sample-and-hold function as a front-end sample-and-hold amplifier in the pipelined ADC and related signal sampling method.
2. Description of the Prior Art
An analog-to-digital converter (ADC) converts an analog signal into a digital signal, and is frequently used in industrial measurement, communication system, and audio/video data processing. ADCs are implemented in the several types including flash ADC, successive approximation ADC, sigma-delta ADC, and pipelined ADC, which are recognized by different sampling rate and resolution. A pipelined ADC can provide both high sampling rate and high resolution, and is widely used in communication system.
Please refer to FIG. 1, which is a block diagram of a 10-bit pipelined ADC 10 according to the prior art. The pipelined ADC 10 includes a sample-and-hold amplifier 100, subsequent stages 102_1-102_8 following the sample-and-hold amplifier (SHA) 100, a flash ADC 104, and an error correction circuit 106. The subsequent stages 102_1 to 102_8 are similar, and only the subsequent stage 102_1 is illustrated as follows. The subsequent stage 102_1 includes a sub-ADC 10, a digital-to-analog converter (DAC) 112, a sample-and-hold unit 114, a subtractor 116, and an amplifier 118, where the DAC 112, the sample-and-hold unit 114, the subtractor 116, and the amplifier 118 consist of a multiplying DAC.
Note that, the front-end sample-and-hold amplifier 100 is used to convert input analog signals into DC-like signals, such that quantization output of the sub-ADC 110 is not influenced easily by noise. However, the sample-and-hold amplifier 100 also brings distortion to the input analog signal of the sub-ADC 110, and costs large power consumption in the pipelined ADC 10. If the sample-and-hold amplifier 100 is not used, when the input analog signal is higher than tens of MHz, sampling points of the sub-ADC 110 may be different from that of the rear-stage multiplying DAC, which causes aperture error, and resolution of the pipelined ADC 10 is therefore reduced.
There are some conventional methods that omit the front-end sample-and-hold amplifier and also reserve the ample-and-hold effect, such as “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC” by Iuri Mehr and Larry Singer, published in IEEE Journal of Solid-State Circuits, vol. 35, no. 3., which implements functions of the front-end sample-and-hold amplifier into the first subsequent stage of a pipelined ADC. Please refer to FIG. 2, which is a schematic diagram of the first subsequent stage 20 of the pipelined ADC disclosed in the mentioned paper. The first subsequent stage 20 includes a sub-ADC 200 and a multiplying DAC 210. The sub-ADC 200 includes two similar comparators 201, 202, and a logic circuit 204, where detail of the comparator 202 is illustrated in FIG. 3. In FIG. 2, the pipelined ADC 210 is illustrated as a single-ended architecture for a simplified presentation, and in fact, the pipelined ADC 210 is a fully differential architecture.
As shown in FIG. 3, the comparator 202 includes a preamplifier 206, a latch circuit 208, switches S1A, S1B, S2A, S2B, S3A, S3B, S4A, S4B, SZ1, SZ2, and capacitors C1-C4, wherein these switches and capacitors forms a switched capacitor circuit, as a sampling circuit, and reference voltages VTH1P, VTH1N, and a common mode voltage VCM are used in the switched capacitor circuit. The preamplifier 206 consists of transistors M1-M6. The multiplying DAC 210 includes a DAC 212, an amplifier 214, switches SM1-SM5, and capacitors CM1 and CM2. For a pipelined ADC of a 1.5-bit/stage architecture, the multiplying DAC 210 requires a positive reference voltage VREFP, a negative reference voltage VREFN and the common mode voltage VCM. The reference voltage VTH1P that the switched capacitor circuit uses is equal to ¼ VREFP, and the reference voltage VTH1N is equal to ¼VREFN. Through the switched capacitor circuit, two threshold voltages, +¼ (VREFP−VREFN) and −¼ (VREFP−VREFN), are generated for the comparison of the comparator 202. As shown in FIG. 3, non-overlapping clock signals Φ1 and Φ2 are used as sampling clocks for two adjacent subsequent stages. Falling edges of clock signals Φ1d and Φ2d are later than falling edges of the clock signals Φ1 and Φ2, respectively. A clock signal Φ2c is a delay clock of the clock signal Φ2d.
When in a sampling phase, the clock signal Φ1 is at a high voltage level, and the switches S1A, S2A, S3A, and S4A are turned on. In this situation, the reference voltages VTH1P and VTH1N are respectively sampled to the capacitors C1-C4, differential input voltages VINP and VINN are sampled to the capacitors C2 and C3, and the switches SZ1 and SZ2 are turned on in order to cancel a DC offset voltage across differential input terminals of the preamplifier 206. In the multiplying DAC 210, an input voltage VIN is sampled to the capacitors CM1 and CM2 when the clock signal Φ1d is at a high voltage level.
When in a holding phase, the clock signal Φ2d is at a high voltage level, and the switches S1B, S2B, S3B, and S4B are turned on. In this situation, a voltage (VINP−VINN) is compared to the threshold voltages +¼ (VREFP−VREFN) and −¼ (VREFP−VREFN), and the voltage across the differential input terminals of the preamplifier 206 indicates a comparison result. The preamplifier 206 amplifies the voltage across the differential input terminals, and the latch circuit 208 latches differential output voltages of the preamplifier 206 at the rising edge of the clock signal Φ2c. Next, the logic circuit 204 generates a 2-bit digital signal as 00, 10, or 11, which indicates different comparison result, according to output voltages latched by the latch circuits of the comparators 200 and 202. In the multiplying DAC 210, the DAC 212 outputs the reference voltages VREFP, VREFN, or VCM to the capacitor CM2 according to the 2-bit digital signal outputted from the logic circuit 204. Briefly, the multiplying DAC 210 amplifies the input voltage VIN and subtracts the outputted reference voltage (which is VREFP, VREFN, or VCM) from the input voltage VIN, to generate a residue voltage VOUT that is outputted to a next subsequent stage.
From the above, the time when the preamplifier 206 performs amplification is between the rising edge of the clock signal Φ2d and the rising edge of the clock signal Φ2c, shown as Td in FIG. 3. In order to prevent the aperture error, a time constant of the switched capacitor circuit in the sub-ADC 200 has to be equal to a time constant of the switched capacitor circuit in the multiplying DAC 210. In other words, resistors and capacitors used in switched capacitor circuits in both sides should fulfill the following equation:
                                                        R              M                        ⁢                          C              M                                =                                                    C                1                                                              G                  m                                +                                  1                  /                                      R                    C                                                                        ≈                                          C                1                                            G                m                                                    ,                            (        1        )            where RM indicates the equivalent resistance of the switch SM1 or SM2; CM indicates the equivalent capacitance of the capacitor CM1 or CM2; Gm is the transconductance of the transistor in the preamplifier 206; RC is the equivalent resistance of the switch in the switched capacitor circuit of the sub-ADC 200. In high-speed applications, the above resistance RC or RM is quite small, so that the transconductance Gm should be large enough to make both sides of the equation 1 to be equal, i.e., the time constants are matched. Note that, a large transconductance Gm causes rise of power consumption of the comparator 202. Also, it is difficult to obtain the matched time constants through adjusting the transconductance of a transistor because the transconductance is not easy to be controlled.